1. Field of the Invention
The present invention generally relates to a NAND-type memory device capable of reducing dimensions of memory cells. More specifically, the present invention is directed to plane arrangements and layer structures of memory cells, bit lines, and bit contacts employed in a memory cell array of a compact NAND-type memory device.
It should be understood in this specification that a NAND-type semiconductor memory device implies such a memory device constructed by NAND-type memory cells in which a plurality of memory transistors are series-connected to each other and are arranged in a matrix form, and each NAND-type memory cell is connected via bit contacts to bit lines connected in an array shape.
2. Description of the Related Art
Referring now to FIG. 1A and FIG. 1B, a description will be made of a plane arrangement and a layer structure of memory cells, bit lines, and bit contacts provided in a memory cell of a conventional NAND-type memory device. FIG. 1A is a plan view for showing a plane arrangement of a conventional NAND-type flash memory device 10. FIG. 1B is a sectional view for indicating a layer structure of this NAND-type flash memory device, taken along a line I--I of FIG. 1A.
In a conventional NAND-type memory device, for instance, in the NAND-type flash memory device 10, as indicated in FIG. 1A, bit lines 12A and 12B connected to the respective memory cells are wired in the array form. Both a bit contact 16A and another bit contact 16B are arranged on one side (namely, right side of memory group in FIG. 1A) of a memory cell group. The bit contact 16A connects a drain region of a memory cell 14A to the bit line 12A. The bit contact 16B connects a drain region of another memory cell (not shown) located adjacent to this memory cell 14A to the bit line 12B. Similarly, bit contacts of all of the bit lines are sequentially arranged on one side of the memory cell group.
Also, as indicated in FIG. 1A and FIG. 1B, a source line 18 is formed by continuing a source region diffusion layer 18. A gate within a memory cell is constituted by a floating gate 20 and a control gate 22 provided via an insulating film with the floating gate 20. Reference numeral 26 shown in FIG. 1A indicates activated regions of the respective memory cells. Reference numeral 24 of FIG. 1B denotes an insulating film.
As indicated in FIG. 1A, a pitch "D" of the bit lines 12 will depend upon an allowable minimum interval (represented as "A" in FIG. 1A) defined when the bit lines 12 are formed, a joint margin (indicated as "B" in FIG. 1A) defined when the bit line 12 is connected to the bit contact 16, and an allowable minimum processing dimension (denoted as "C" in FIG. 1A) of the bit control. This pitch "D" is expressed by: EQU D=A+2.times.B+C.
In other words, in the conventional bit line plane arrangement, the necessary dimension of the memory cell array along the word line (control gate) direction, namely the necessary dimension along a direction perpendicular to the bit line is necessarily restricted, or constrained by the pitch dimension of the bit line, i.e., D=A+2.times.B+C. Even when the width dimension of the memory cell may be reduced, the dimension of the memory cell array along the word line direction could not be reduced unless the pitch dimension of the bit lines could be decreased. As a consequence, a recognition could be made of such a fact that the pitch dimension of the pitch lines should be reduced in order to reduce the memory array. However, the respective dimensions of the above-described factors "A", "B", and "C" for defining the pitch dimension are nowadays set to the minimum dimensions thereof. Accordingly, there are various technical difficulties to further reduce these minimum dimensions.
On the other hand, while semiconductor devices are rapidly made in very fine dimensions and higher integration, a similar demand is made of NAND-type memory devices to be manufactured in very fine dimensions and high integration.
Therefore, an object of the present invention is to provide a NAND-type memory device having a small-sized memory array by arranging bit contacts in such a manner that a pitch dimension can be shortened.